The present specification relates generally to the field of integrated circuits and to methods of manufacturing and modeling the manufacture of integrated circuits. More particularly, the present specification relates to improving the accuracy of model based optical proximity correction (OPC).
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation (such as light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Sub-wavelength lithography places large burdens on lithographic processes. Resolution of anything smaller than a wavelength in any field of wave analysis is quite difficult. Pattern fidelity can deteriorate quite dramatically in sub-wavelength lithography. This deterioration can occur through a combination of effects, including distortions inherent in the formation of the optical image, effects arising from the chemical and physical interaction of the photoresist and developer, and loading variations in the etching process. Alone or in concert, these effects can cause the features as formed to deviate significantly in size and shape from the ideal pattern as drawn by the circuit designer. Circuit performance and chip yield can be significantly affected by these distortions in feature size and placement.
There are many different design rules which give instructions to circuit designers on how to avoid these process regions altogether, by setting minimum sizes for certain features or spaces. Design-rule-checking (DRC) software is used to automatically verify that all IC designs adhere to this set of design rules. However, to continue to obtain smaller dimensions, features must be made smaller than these typical minimum settings.
One solution which purports to be a guide to navigate the non-linearities and distortions in these process regions is called an xe2x80x9coptical rules checkerxe2x80x9d (ORC). The ORC is a software product that evaluates a design for anticipated manufacturability. The chief function of the ORC is to identify problem areas in the design that will lead to performance reduction or yield loss. This identification is done by comparing IC designs with predictions of the corresponding silicon manufacturing results and calculating the edge placement error (EPE) expected. Severe EPE results indicate a design which may have significant fabrication problems.
Two problems of integrated circuit fabrication design are of particular concern. The first is a simple problem of one-dimensional line-width control. In different regions on the chip, depending on the local density of features, gates and interconnect lines that are drawn to be the same nominal dimension have different physical sizes. This inconsistency can, in turn, degrade the overall speed specification and reduce the yield of an IC fabrication process.
The second problem is the pullback of line ends from their nominal position. This is sometimes called a xe2x80x9c1.5-D Proximity Problemxe2x80x9d. When lines do not end where expected, overlap with contacts and vias will be reduced, driving current densities higher and causing possible failures or shorts in the design.
The pattern fidelity problems described above are very repeatable, and can be systematically characterized. An ORC check can describe the magnitude of the problem, but to solve the problem, the design layout must be manipulated using specialized EDA (Electronic Design Automation) software. This correction procedure is generally designated by the abbreviation xe2x80x9cOPCxe2x80x9d. Originally OPC stood for xe2x80x9coptical proximity correctionxe2x80x9d, because the most obvious distortions requiring correction were optical in origin. However, the mathematical description of a process can also incorporate effects from several process steps, including photoresist development and etch effects. The initials xe2x80x9cOPCxe2x80x9d can therefore be more broadly used to represent xe2x80x9coptical and process correctionsxe2x80x9d, more accurately reflecting the practice of OPC as it is done today.
Using empirical data, OPC software creates a mathematical description of the process distortions. This description can be in the form of simple shape manipulation rules, or a more detailed and intricate process model. Once this description is generated, automated software changes the shapes of the polygons in the pattern layout files, moving segments of line edges and adding features that compensate the layout for the distortions to come. The critical levels of the photomask set can then be made using these modified, xe2x80x9cpredistortedxe2x80x9d layout designs. When these masks are used to make chips, these predistortions will cancel the process distortions, resulting in better pattern fidelity, higher yield, and enhanced chip performance. This xe2x80x9cpredistortionxe2x80x9d is the core of OPC technology.
The idea of precompensation or pre-distortion is not new to IC lithography, including the use of serifs (fine lines finishing off the main strokes of a letter or geometric shape) and sub-resolution assist features for better pattern fidelity. Global line-width biasing for process compensation and the use of serifs crafted onto line ends in memory cells have been employed to enhance the ability to make these structures. These techniques have not been widely adopted for ICs in general, however, because their reliance on hand-crafted design manipulations made them practical only for addressing specific problems in repeating layouts, such as memory cells.
A more systematic approach to this correction procedure has now become possible with the advent of sophisticated process simulation techniques and modern data manipulation tools. Numerical models for lithographic imaging and semiconductor process simulation have significantly improved in both accuracy and speed in recent years and can now be integrated with an iterative OPC technique. This in turn can be integrated with EDA software techniques for managing large databases of polygons that represent hierarchical IC designs. The result is an efficient OPC tool for layout manipulation that adjusts the design for optimum manufacturability.
OPC corrections can be added in a range of styles or degrees of xe2x80x9caggressivenessxe2x80x9d that can be tailored to suit the lithographic problems at hand. For relatively mild problems, the solutions can be described by a simple set of rules for design manipulations, which can be implemented using standard verification tools. For processes with mild distortions, this can be sufficient to address more than 50% of the pattern fidelity problems.
These rules are derived from a set of empirical observations about process behavior, and are usually quite straightforward to implement. However, with real processes, experienced users begin to see variations in the efficacy of these rules depending on the local layout context, due to the influence of nearby layout features or a general local pattern density. They respond by making a more elaborate set of rules, to begin to address each of these special cases, and the descriptions become unwieldy. In this case, a more general description of the process, or process model, becomes the more efficient technique.
For model-based correction, the problems encountered are in fact similar to those generically encountered when an image is transmitted through a distorting medium. The mathematics of such situations has been well characterized for many years. From a number of straightforward measurements using a well-crafted test pattern, general distortion functions that describe the overall process behavior can be produced. These descriptions are quite abstract, and can be generated from empirical measurements alone without specific reference to individual process parameters. With this process model in hand, the edges of the original design polygons in the design can then be adjusted and manipulated until the predictions of edge placement errors using these process models converge. The final layout is then converted to a mask layout, using jogs, biases, serifs, and other pattern manipulations compatible with the mask fabrication process.
Conventional commercialized OPC tools cannot, nevertheless, anticipate or expect bridging patterns and/or line-shortening effects for areas below 0.15 xcexcm design rule. Bridging patterns are closely spaced features on a photoresist pattern that are connected once they are transferred to the IC wafer. Line-shortening occurs when the size of the transferred pattern on the IC wafer is shorter than the pattern on the photoresist. In general, model based OPC utilizes modified aerial image simulation by adding empirical (experimental) data at best exposure dose and at best focus condition. Empirical data, however, includes only limited sample test patterns. As such, model based OPC is only an approximation. Using conventional model based OPC does not prevent critical dimension (CD) measurement error and mask CD error. Thus, inaccuracies of model based OPC can come from the inaccuracy of empirical data and measurements.
In general, empirical data for OPC is generated by the following process. First, an OPC tool finds a best exposure dose and focus condition for target CD and pitch using optimized stepper NA and sigma (partial coherence) condition. Next, the OPC tool measures sample CDs using standard test design, standard test design is dependent on the target CD or target design rule. Based from these sample CDs, an equation or parameters can be created. Such an equation or parameters are dependent on the commercialized OPC tool used by the IC designer.
After empirical data is created, the OPC tool modifies the original aerial image intensity. Based on these modified aerial image intensity contour, pattern deformation (e.g., corner rounding, line-end shortening, bridging, CD bias . . . ) by proximity effect of original design can be corrected. Next, the design corrected by the OPC tool is taped out to the mask shop for fabrication of a reticle. If the target CD on the mask of this reticle is exactly same as target CD using standard test reticle, there will be no problem. But, usually, the mask CD of these two reticles (standard test reticle and OPC reticle) are different.
Thus, the inaccuracy of model based OPC can be a result of (1) the selected exposure dose and focus not being at best condition such that CD measurement data on the wafer is not accurate, (2) there are mask CD errors between the two reticles used in the design process, and/or (3) the model algorithm of each company is not accurate.
Thus, there is a need for a method to improve the accuracy of model based OPC. Further, there is a need to reduce the CD measurement error on an IC wafer. Yet further, there is a need to reduce mask CD errors on a reticle.
An exemplary embodiment relates to a method of improving the accuracy of model-based optical proximity correction (OPC). This method can include identifying best exposure dose and best focus conditions, measuring critical dimensions at the identified conditions, measuring critical dimensions at variations from the identified conditions, and obtaining critical dimension information by averaging measured critical dimensions.
Another exemplary embodiment relates to a method of improving the critical dimension (CD) measurement error on integrated circuit wafers and mask CD errors on reticles in an integrated circuit fabrication process. This method can include selecting a condition which provides a best exposure dose and a best focus, measuring critical dimensions on an integrated circuit wafer and on a reticle at the selected condition, measuring critical dimensions on the integrated circuit wafer and on the reticle at a different exposure dose than the best exposure dose, measuring critical dimensions on the integrated circuit wafer and on the reticle at a different focus than the best focus, and averaging measured critical dimensions at the selected condition, at the different exposure dose, and at the difference focus.
Another exemplary embodiment relates to a method of improving critical dimension (CD) errors in an integrated circuit fabrication process. This method includes selecting an exposure dose and focus at a best condition and measuring critical dimensions at various exposure dose and focus conditions including the selected exposure dose and focus condition.